1. Field of the Invention
The invention relates to a memory accessing technique, and more particularly, to a technique of correcting erroneous data stored in a memory.
2. Description of the Prior Art
Please refer to FIG. 1, which is a functional block diagram of an error correction device 100 cooperating with other function units 130 in a conventional DVD player. As shown in FIG. 1, the error correction device 100 comprises a decoding unit 110 and an error correction unit 120. In this case, the decoding unit 110 is a Reed-Solomon product code (RSPC) decoder for reading data from the main memory 150 through a system bus 140 and executing PI/PO decoding to obtain a plurality of error values and a plurality of error addresses corresponding to said error values. In addition, the error correction unit 120 reads error data from the memory 150 through the system bus 140 according to the error addresses, performs a logical or arithmetical calculation (normally an XOR logic), and then rewrites the calculated correct data into the error address of the memory 150 to overwrite the error data. Therefore, error data stored in the memory 150, which are read from the DVD disc, can be corrected.
As mentioned previously, after the decoding unit 110 obtains the error values and error addresses during the PI/PO decoding operations, the operation of the error correction unit 120 can be illustrated by the following three steps: step (1) reading error data corresponding to a specific error address from the memory 150 through the system bus 140; step (2) performing an error correction logical or arithmetical calculation on the read error data and the error value corresponding to the specific error address; and step (3) writing the result (that is, the correct data) of the calculation back into the error address of the memory 150. Basically, the system is designed to utilize the system bus 140 in the most efficient manner. Therefore, an arbitrator 160 is used to manage the priority of access to the system bus 140 of each function unit, including the error correction device 100. In other words, the system bus 140 is utilized more efficiently by adopting the arbitrator 160. Under the above-mentioned principle, before the error correction unit 120 performs step (1), the error correction unit 120 needs to issue a request to the arbitrator 160 for gaining access to the system bus 140. Furthermore, after finishing the process of reading the error data, the error correction unit 120 will release control of the system bus 140, such that other function units can utilize the system bus 140. Moreover, after the operations of step (2) and before the operations of step (3), the error correction unit 120 will again issue a request to the arbitrator 160, gaining access to the system bus 140, to write the correct data. After the correct data are written into the memory 150, the system bus 140 will again be released such that other function units can utilize the system bus 140.
As known by those skilled in the art, in DRAM when data corresponding to an inactive row needs to be accessed, a change row operation will be performed. Every time when the change row operation is performed, the memory must spend considerable prerequisite preparation time, such as precharge time, active time, and read delay/write delay. After finishing step (1) or step (3), the above-mentioned error correction device 100 releases control of the system bus 140 for other function units' use, and it is likely that these other function units 130 will access the main memory 150 when they have obtained control of the bus. Unfortunately, most of the time, the function units 130 access data in different rows of the main memory 150. This causes frequent change row actions, and thus excessive time spent on data access preparation, for consecutively performed error correction operations. The entire system efficiency is downgraded as a result.